In recent years, along with miniaturization and high integration of semiconductor integrated circuits, fluctuations of delay time due to variations (hereinafter, referred to as process variation) in gate length and gate width, or variations (hereinafter, referred to as wiring variation) in wiring length and wiring width in transistors of semiconductor integrated circuits increase. To cope with the above, a technology in which a burden of a timing verification to verify the above-described variations of the delay time is suppressed from increasing is considered.
In the timing verification, for example, whether timing between a data signal supplied to a register (flip-flop) and a clock signal satisfies a timing restriction is verified. When the timing fails to satisfy the timing restriction, for example, a delay buffer with a large delay is inserted into a data path to transfer a data signal or a clock path to transfer a clock signal to thereby adjust the delay time.    Japanese Laid-open Patent publications No. 2009-110380    Japanese Laid-open Patent publications No. 2008-21134
However, a wiring within the delay buffer is short, and a difference between a path into which the delay buffer is inserted and other paths may be caused in fluctuations in the delay time due to the wiring variation. Therefore, depending on relationships between the process variation and the wiring variation in transistors, a timing margin (slack) allowable between a data signal and a clock signal, which are supplied to a register, largely fluctuates, and as a result, a timing violation occurs.